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datasheet femtoclock ? crystal-to-lvds clock generator ics844201-45 ics844201bg-45 revision a october 1, 2013 1 ?2013 integrated device technology, inc. general description the ics844201-45 is a pci express tm clock generator. the ics844201-45 can synthesize 100mhz or 125mhz reference clock frequencies with a 25mhz crystal. the ics844201-45 has excellent phase jitter performance and is packaged in a small 8-pin tssop, making it ideal for use in systems with limited board space. features ? one differential lvds output ? crystal oscillator interface designed for 18pf, 25mhz parallel resonant crystal ? vco range: 490mhz ? 680mhz ? rms phase jitter at 100mhz (12k hz ? 20mhz): 0.792ps (typical) ? rms phase jitter at 125mhz (12k hz ? 20mhz): 0.773ps (typical) ? full 3.3v output supply mode ? pci express (2.5gb/s) and gen 2 (5gb/s) jitter compliant ? 0c to 70c ambient operating temperature ? lead-free (rohs 6) packaging frequency table inputs output frequency range (mhz) crystal frequency (mhz) m fsel n multiplication value m/n 25 20 1 4 5 125 (default) 25 20 0 5 4 100 1 2 3 4 8 7 6 5 gnd xtal_out xtal_in fsel q nq v dd nc pin assignment ics844201-45 8 lead tssop 4.40mm x 3.0mm x 0.925mmpackage body g package top view osc phase detector vco 490mhz - 680mhz m = 20 (fixed) n = 5 4 (default) q nq pullup xtal_in xtal_out fsel block diagram
ics844201bg-45 revision a october 1, 2013 2 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator pin descriptions and characteristics table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of the product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating c onditions for extended periods may affect product reliability. number name type description 1 gnd power power supply ground. 2, 3 xtal_out xtal_in input crystal oscillator interface. xtal_in is the input, xtal_out is the output. 4 fsel input pullup frequency select pin. lvcmos/lvttl interface levels. 5 nc unused no connect. 6v dd power power supply pin. 7, 8 nq, q output differential outp ut pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? item rating supply voltage, v dd 4.6v inputs, v i xtal_in other inputs 0v to v dd -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma package thermal impedance, ? ja 129.5 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c
ics844201bg-45 revision a october 1, 2013 3 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator dc electrical characteristics table 3a. power supply dc characteristics, v dd = 3.3v 10%, t a = 0c to 70c table 3b. lvcmos/lvttl dc characteristics, v dd = 3.3v 10%, t a = 0c to 70c table 3c. lvds dc characteristics, v dd = 3.3v 10%, t a = 0c to 70c table 4. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 2.97 3.3 3.63 v i dd power supply current 95 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current v dd = v in = 3.63v 5 a i il input low current v dd = 3.63v, v in = 0v -150 a symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v diff_out peak-to-peak differential output voltage 494 908 mv v os offset voltage 1.3 1.63 v ? v os v os magnitude change 50 mv parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 24.5 25 34 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf
ics844201bg-45 revision a october 1, 2013 4 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator ac electrical characteristics table 5. ac characteristics, v dd = 3.3v 10%, t a = 0c to 70c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: characterized using a 25mhz crystal. note 1: refer to phase noise plots. note 2: peak-to-peak jitter after applying system transfer func tion for the common clock architecture. maximum limit for pci ex press gen 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. see idt application note pci express reference clock requirements and also the pci express application section of this datasheet which show each individual transfer function and the overall composite tr ansfer function. note 3: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architectu re and reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0 ps rms for t refclk_lf_rms (low band). see idt application note pci express reference clock requirements and also the pci express application section of this datasheet which sh ow each individual transfer function and the overall composite tr ansfer function. symbol parameter test conditio ns minimum typical maximum units f out output frequency 125 mhz 100 mhz t jit(?) rms phase jitter, random; note 1 125mhz, integration range: 12khz ? 20mhz 0.773 ps 100mhz, integration range: 12khz ? 20mhz 0.792 ps t j phase jitter peak-to-peak; note 2 125mhz, (1.2mhz ? 21.9mhz 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 12.51 ps 100mhz, (1.2mhz ? 21.9mhz) 25mhz crystal input evaluation band: 0hz - nyquist (clock frequency/2) 13.48 ps t refclk_hf_rms phase jitter rms; note 3 125mhz, (1.2mhz ? 21.9mhz) 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 1.13 ps 100mhz, (1.2mhz ? 21.9mhz) 25mhz crystal input high band: 1.5mhz - nyquist (clock frequency/2) 1.25 ps t refclk_lf_rms phase jitter rms; note 3 125mhz, (1.2mhz ? 21.9mhz) 25mhz crystal input low band: 10khz - 1.5mhz 0.32 ps 100mhz, (1.2mhz ? 21.9mhz) 25mhz crystal input low band: 10khz - 1.5mhz 0.33 ps t r / t f output rise/fall time 20% to 80% 250 450 ps odc output duty cycle f out = 125mhz 48 52 % f out = 100mhz 46 54 %
ics844201bg-45 revision a october 1, 2013 5 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator typical phase noise at 100mhz typical phase noise at 125mhz 100mhz rms phase jitter (random) 12khz to 20mhz = 0.792ps (typical) noise power (dbc/hz) offset frequency (hz) 125mhz rms phase jitter (random) 12khz to 20mhz = 0.773ps (typical) noise power (dbc/hz) offset frequency (hz)
ics844201bg-45 revision a october 1, 2013 6 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator parameter measureme nt information 3.3v lvds output load ac test circuit output rise/fall time offset voltage setup differential output voltage rms phase jitter output duty cycle/pulse width/period differential output voltage setup scope qx nqx 3.3v10% power supply +? float gnd v dd 20% 80% 80% 20% t r t f v od nq q v od 380mv (typical) v diff_out 760mv (typical) nq q
ics844201bg-45 revision a october 1, 2013 7 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator application information crystal input interface the ics844201-45 has been characterized with 18pf parallel resonant crystals. the capacitor values, c1 and c2, shown in figure 1 below were determined using a 25mhz, 18pf parallel resonant crystal and were chosen to minimize the ppm error. the optimum c1 and c2 values can be slightly adjusted for different board layouts. figure 1. crystal input interface xtal_in xtal_out x1 18pf parallel crystal c1 27pf c2 27pf
ics844201bg-45 revision a october 1, 2013 8 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator overdriving the xtal interface the xtal_in input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the xtal_out pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be less than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal interference with the power rail and to reduce internal noise. figure 2a shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this c onfiguration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and changing r2 to 50 ? . the values of the resistors can be increased to reduce the loading for a slower and weaker lvcmos driver. figure 2b shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the xtal_in input. it is recommended that all components in the schematics be placed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 2a. general diagram for lvcmos driver to xtal input interface figure 2b. general diagram for lvpec l driver to xtal input interface vcc xtal_out xtal_in r1 100 r2 100 zo = 50 ohms rs ro zo = ro + rs c1 .1uf lvcmos driver xta l _ o u t xta l _ i n zo = 50 ohms c2 .1uf lvpecl driver zo = 50 ohms r1 50 r2 50 r3 50
ics844201bg-45 revision a october 1, 2013 9 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output struct ures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the out put structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. lvds termination lvds driver lvds driver lv d s receiver lv d s receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination
ics844201bg-45 revision a october 1, 2013 10 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator pci express application note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase in terpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiv er is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the ent ire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s ?? h3 s ?? h1 s ?? h2 s ?? ? ?? ? = ys ?? xs ?? h3 s ?? ? h1 s ?? h2 s ?? ? ?? ? =
ics844201bg-45 revision a october 1, 2013 11 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator schematic example figure 4 shows an example of ics844201-45 application schematic. in this example, the device is operated at v dd = 3.3v. the 18pf parallel resonant 25mhz crystal is used. the c1 = 27pf and c2 = 27pf are recommended for frequency accuracy. for different board layouts, the c1 and c2 may be slightly adjusted for optimizing frequency accuracy. two examples of lvds for receiver without built-in termination are shown in this schematic. figure 4. ics844201-45 schematic example zo = 50 ohm c9 0.1uf x1 25 mhz to logic input pins set logic input to '0' u1 1 2 3 4 8 7 6 5 gnd xta l _ o u t xta l _ i n fsel q nq vdd nc + - vdd r1 100 zo = 50 ohm vdd fsel c3 0.01u to logic input pins logic input pin examples ru2 not install zo = 50 ohm q c1 27pf rd1 not install xta l _ i n + - q xta l _ o u t set logic input to '1' ru1 1k 1 8 p f vdd=3.3v c2 27pf r4 50 nq zo = 50 ohm rd2 1k alternate lvds terminat ion vdd r3 50 nq
ics844201bg-45 revision a october 1, 2013 12 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator power considerations this section provides information on power dissipa tion and junction temperature for the ics844201-45. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics844201-45 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 10% = 3.63v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 3.63v * 95ma = 344.85mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate va lue is 129.5c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.345w * 129.5c/w = 114.7c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 8 lead tssop, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 129.5c/w 125.5c/w 123.5c/w
ics844201bg-45 revision a october 1, 2013 13 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator reliability information table 7. ? ja vs. air flow table for a 8 lead tssop transistor count the transistor count for ics844201-45 is: 1986 package outline and package dimensions package outline - g suffix for 8 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 129.5c/w 125.5c/w 123.5c/w all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10
ics844201bg-45 revision a october 1, 2013 14 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator ordering information table 9. ordering information part/order number marking package shipping packaging temperature 844201BG-45LF 4b45l ?lead-free? 8 lead tssop tube 0c to 70c 844201BG-45LFt 4b45l ?lead-free? 8 lead tssop tape & reel 0c to 70c
ics844201bg-45 revision a october 1, 2013 15 ?2013 integrated device technology, inc. ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator revision history sheet rev table page description of change date a t9 1 8 9 10 12 14 changed femtoclock? to femtoclock ? . deleted hyperclock image in the first paragraph. updated the overdriving the xtal interface note. updated the lvds driver termination note. updated the pci express application note. power considerations: deleted 'note: please refer to section 3 for details on calculating power dissipated in the load.' deleted quantity from tape & reel. deleted lead-free note. deleted disclaimer. 10/1/2013
ics844201-45 data sheet femtoclock ? crystal-to-lvds clock generator disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution

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